The present invention relates to a method for fabricating a semiconductor integrated circuit device including field effect transistors (FETS) and capacitors that are integrated together on the same semiconductor substrate.
Hereinafter, a known method for fabricating a semiconductor integrated circuit device including FET and capacitor on the same substrate will be described with reference to FIGS. 7A through 7E.
First, although not shown, a channel region and respective doped regions to be source/drain regions are defined in predetermined regions within a semiconductor substrate 1. Next, the surface of the substrate 1 is coated with a resist film, which is then patterned by a phase-shifting technique. In this manner, a fine-line resist pattern 2 is formed in a region on the substrate 1 (i.e., a region over the channel region) where a gate electrode will be formed, as shown in FIG. 7A.
Subsequently, as shown in FIG. 7B, an insulating film 3 of silicon dioxide is deposited over the entire surface of the substrate 1 and the resist pattern 2 is lifted off. As a result, an opening 3a is formed in the insulating film 3 for the gate electrode of an FET. In this specification, this opening 3a will be called a "gate electrode opening" for convenience sake.
Then, as shown in FIG. 7C, a lower electrode 4A is formed in a region over the insulating film 3 where a capacitor will be formed. Thereafter, as shown in FIG. 7D, a strontium titanate (SrTiO.sub.3) film 5 and a metal film 6 are deposited in this order by plasma-enhanced RF sputtering over the entire surface of the insulating film 3 as well as over the lower electrode 4. In the next process step, these films 5 and 6 will be shaped into capacitive insulating film and upper electrode, respectively.
Next, the metal film 6 and SrTiO.sub.3 film 5 are wet-etched, thereby forming the upper electrode 6A and capacitive insulating film 5A, respectively, as shown in FIG. 7E.
Finally, as shown in FIG. 7F, metallization is carried out to fill in the opening 3a of the insulating film 3 and thereby form a gate electrode 7. Also, ohmic electrodes 8 are formed as source/drain electrodes on right- and left-hand sides of the gate electrode 7. As a result, a conventional semiconductor integrated circuit device including FET and capacitor is obtained.
The prior art method, however, has the following drawbacks. Specifically, in the process step shown in FIG. 7D of depositing the SrTiO.sub.3 film 5 by plasma-enhanced RF sputtering, a surface region of the substrate 1, e.g., the channel region, in particular, is unintentionally exposed to the plasma through the gate electrode opening 3a of the insulating film 3. Then, crystal imperfections are caused in the channel region to considerably decrease the mobility of electrons traveling therethrough. Specifically, once the SrTiO.sub.3 film 5 is deposited, the electron mobility in the channel region decreases from about 5500 cm.sup.2 /V.multidot.sec. to about 3200 cm.sup.2 /V.multidot.sec. As a result, the operating characteristics of the FET deteriorate.
It is not impossible to prevent the substrate 1 from being exposed to the plasma through the gate electrode opening 3a by depositing the SrTiO.sub.3 film 5 before the opening 3a has been formed in the insulating film 3. However, another problem arises in such a case. This new problem will be described below with reference to FIG. 8.
According to this alternate technique, a capacitor, consisting of the lower electrode 4A, capacitive insulating film 5A and upper electrode 6, is formed on the insulating film 3 that has been deposited on the semiconductor substrate 1. Then, the entire surface of the substrate 1 is coated with a resist film 9 as shown in FIG. 8. In such a case, a level difference exists between the capacitor and surrounding regions thereof on the insulating film 3, and the thickness of the resist film 9 is non-uniform. Thus, if the resist film 9 is irradiated with exposing radiation L.sub.E to provide a gate electrode opening 9a in the resist film 9, the exposing radiation L.sub.E, which has passed through the resist film 9, is diffused by the level difference portion of the capacitor toward the surrounding regions. As a result, the opening 9a of the resist film 9 has its size increased or decreased from the desired one due to the reflected radiation L.sub.R. Accordingly, if the insulating film 3 is etched to form the gate electrode opening 3a therethrough using the resist film 9 with such an opening 9a as a mask, then the size of the resulting gate electrode opening 3a deviates from the predetermined value. This problem gets even more serious when the resist film 9 is provided with the opening 9a by a phase-shifting technique.
Thus, to provide a gate electrode opening of a very small size for the insulating film 3, the capacitor has to be formed after the gate electrode opening 3a has been provided in the insulating film 3, not before.